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MPC105EC/d (motorola order number) 5/95 the powerpc name, powerpc logotype, powerpc 601, powerpc 603, powerpc 604, and powerpc architecture are trademarks of international business machines cirp. used by motorola under license from international business machines corp. this document contains information on a new product under development by motorola. motorola reserves the right to ? change or discontinue this product without notice. motorola inc. 1995. all rights reserved. 105 hardware speci?ations advance information mpc105 pci bridge/memory controller hardware speci?ations the mpc105 provides a powerpc ? reference platform compliant-bridge between the powerpc microprocessor family and the peripheral component interconnect (pci) bus. this document contains pertinent physical characteristics of the mpc105. for functional characteristics refer to the mpc105 pci bridge/memory controller users manual . this document contains the following topics: topic page section 1.1, ?pc105 overview? 2 section 1.2, ?eneral parameters? 3 section 1.3, ?pc105 electrical and thermal characteristics? 4 section 1.4, ?pc105 pinout diagram? 12 section 1.5, ?pc105 package description? 17 section 1.6, ?ystem design information 19 in this document, the term ?0x?is used to denote a 32-bit microprocessor from the powerpc architecture ? family. 60x processors implement the powerpc architecture as it is speci?d for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and ?ating-point data types of 32 and 64 bits (single-precision and double-precision).
2 105 hardware specifications preliminary/subject to change without notice 1.1 mpc105 overview the mpc105 provides a powerpc reference platform-compliant bridge between powerpc 601 ? , powerpc 603 ? , and powerpc 604 ? microprocessors and the pci bus. pci support allows system designers to rapidly design systems using peripherals already designed for pci and the other standard interfaces available in the personal computer hardware environment. the mpc105 integrates secondary cache control and a high-performance memory controller that supports dram, synchronous dram (sdram), rom, and flash rom. the mpc105 uses an advanced, 3.3 v cmos process technology and is fully compatible with ttl devices. the mpc105 supports a programmable interface to a variety of powerpc microprocessors operating at various bus speeds. the mpc105s 60x interface allows for a variety of system con?urations by providing support for either a second processor or a secondary (l2) cache. the l2 cache control unit generates the arbitration and support signals necessary to maintain a write-through or write-back lookaside cache. the mpc105s pci interface is designed to connect the processor and memory system to the pci local bus without the need for ?lue?logic. the mpc105 acts as both a master and slave device on the pci bus. the memory interface controls processor and pci interactions to main memory. it is capable of supporting a variety of dram or sdram, and rom or flash rom con?urations. the mpc105 provides hardware support for four levels of power reduction?ap, doze, sleep, and suspend. the mpc105s design is fully static, allowing internal logic states to be preserved during all power saving modes. 1.1.1 mpc105 features major features of the mpc105 are as follows: processor interface 60x processors supported at a wide range of frequencies 32-bit address bus con?urable 64- or 32-bit data bus accommodates an upgrade of either an external l2 cache or a secondary processor arbitration for secondary processor on-chip full memory coherency supported pipelining of 60x accesses store gathering on 60x-to-pci writes secondary (l2) cache control con?urable for write-through or write-back operation 256k, 512k, 1m sizes up to 4 gbytes of cacheable space direct-mapped parity supported supports external byte decode or on-chip byte decode for write enables programmable timing supported synchronous burst and asynchronous srams supported
105 hardware specifications 3 preliminary/subject to change without notice pci interface compliant with pci local bus speci?ation, revision 2.0 supports pci interlocked accesses to memory using lock signal and protocol supports accesses to all pci address spaces selectable big- or little-endian operation store gathering on pci writes to memory selectable memory prefetching of pci read accesses only one external load presented by the mpc105 to the pci bus pci con?uration registers interface operates at 16?3 mhz data buffering (in/out) parity supported 3.3 v/5.0 v compatible concurrent transactions on 60x and pci buses supported memory interface programmable timing supported supports either dram or sdram high bandwidth (64-bit) data bus supports self-refreshing dram in sleep and suspend modes supports 1 to 8 banks built of x1, x4, x8, x9, x16, or x18 drams supports powerpc reference platform-compliant contiguous or discontiguous memory maps 1 gbyte of ram space, 16 mbytes of rom space supports 8-bit asynchronous rom or 32-/64-bit burst-mode rom supports writing to flash rom con?urable external buffer control logic parity supported ttl compatible power management fully-static 3.3 v cmos design supports 60x nap, doze, and sleep power management modes, and suspend mode ieee 1149.1-compliant, jtag boundary-scan interface 304-pin ball grid array (bga) package 1.2 general parameters the following list provides a summary of the general parameters of the mpc105. technology 0.5 m m cmos, four-layer metal chip size 6.69 mm x 5.82 mm (38.9 mm 2 ) chip performance 25 mhz, 33.33 mhz, 50 mhz, and 66.67 mhz package surface mount 304-pin c4 ceramic ball grid array (cbga) power supplies 3.3 v 5% maximum input rating 5.0 v 10%
4 105 hardware specifications preliminary/subject to change without notice 1.3 mpc105 electrical and thermal characteristics this section provides both the ac and dc electrical speci?ations and thermal characteristics for the mpc105. the following speci?ations are preliminary and subject to change without notice. for the most recent speci?ations, contact your local motorola sales of?e. 1.3.1 dc electrical characteristics table 1 and table 2 provide the absolute maximum rating and thermal characteristics for the mpc105. table 3 provides the dc electrical characteristics for the mpc105. table 1. absolute maximum ratings characteristic symbol value unit supply voltage vdd ?.3 to 3.6 v input voltage v in ?.3 to 5.5 v junction temperature t j 0 to 105 c storage temperature range t stg ?5 to 150 c notes: 1. functional operating conditions are given in table 3. absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution: input voltage must not be greater than the supply voltage by more than 2.5 v at all times including during power-on reset. table 2. thermal characteristics characteristic symbol value rating cbga package thermal resistance, junction to case q jc 0.133 c/w note: t j = t a + p d x q ja where q ja = q jc + q ca, see section 1.6, ?ystem design information,?for additional information. table 3. dc electrical specifications vdd = 3.3 5% vdc, gnd = 0 vdc characteristic symbol min max unit input high voltage (all inputs except sysclk) v ih 2 5.5 v input low voltage (all inputs except sysclk) v il gnd 0.8 v sysclk input high voltage cv ih 2.4 5.5 v sysclk input low voltage cv il gnd 0.4 v input leakage current i in ?0 m a hi-z (off-state) leakage current i tsi ?0 m a output high voltage, i oh = 18 ma v oh 2.4 v
105 hardware specifications 5 preliminary/subject to change without notice table 4 provides the power dissipation for the mpc105. 1.3.2 ac electrical characteristics this section provides the clock ac electrical characteristics for the mpc105. 1.3.2.1 input ac speci?ations table 5 provides the clock ac timing speci?ations as de?ed in figure 1. these speci?ations are for operation between 16.67 and 33.33 mhz bus clock (sysclk) frequencies. output low voltage, i ol = 14 ma v ol 0.5 v capacitance, v in = 0 v, f = 1 mhz 1 c in ? pf note: 1. capacitance is periodically sampled rather than 100% tested. table 4. power dissipation 1 sysclk/internal clock frequency (mhz) power management mode 25/25 33.33/33.33 25/50 33.33/66.67 unit max values (vdd = 3.47 v) full-on mode 0.60 0.8 1.30 1.70 w doze mode tbd tbd tbd tbd mw nap mode tbd tbd tbd tbd mw sleep mode 2 140 180 220 260 mw suspend mode 3 50 50 90 90 mw typical values (vdd = 3.3 v) full-on mode 0.40 0.50 0.70 0.90 w doze mode tbd tbd tbd tbd mw nap mode tbd tbd tbd tbd mw sleep mode 2 70 110 140 180 mw suspend mode 3 30 30 60 60 mw notes: 1. power dissipation for common system con?urations assuming 50 pf loads 2. power saving modes assume system clock off. 3. suspend power saving mode assumes system clock off and pll in clock bypass mode. table 3. dc electrical specifications (continued) vdd = 3.3 5% vdc, gnd = 0 vdc characteristic symbol min max unit
6 105 hardware specifications preliminary/subject to change without notice figure 1. sysclk input timing diagram 1.3.2.2 input ac speci?ations table 6 provides the input ac timing speci?ations for the mpc105 as de?ed in figure 2 and figure 3. these speci?ations are for operation between 16.67 and 33.33 mhz bus clock (sysclk) frequencies. table 5. clock ac timing specifications vdd = 3.3 5% vdc, gnd = 0 vdc num characteristic min max unit notes frequency of operation 16.67 33.33 mhz 1 sysclk cycle time 30.0 60.0 ns 2,3 sysclk rise and fall time 2.0 ns 1 4 sysclk duty cycle measured at 1.4 v 40.0 60.0 % 5a sysclk pulse width high measured at 1.4 v 12 18 ns 2 5b sysclk pulse width low measured at 1.4 v 12 18 ns 2 6 sysclk frequency stability 1000 ppm 7 sysclk jitter 150 ps 3 8 mpc105 internal pll relock time 100 m s4 9 phase-lock loop vco operating range 120 200 mhz 5 notes: 1. rise and fall times for the sysclk input are measured from 0.4 v to 2.4 v. 2. speci?ation value is at maximum frequency of operation. 3. cycle-to-cycle jitter 4. relock timing is guaranteed by design and is not tested. 5. for con?uration of the vco, see table 10. 5a 5b vm vm = midpoint voltage (1.4 v) 2 3 cv il cv ih 1 sysclk vm vm
105 hardware specifications 7 preliminary/subject to change without notice table 6. input ac timing specifications vdd = 3.3 5% vdc, gnd = 0 vdc num characteristic min max unit notes 10 a0?31, par0?ar7, tt0?t4, aack , t a , gbl , ci , wt , tv input valid to sysclk (input setup) 4.0 ns 1 11 dl0?l31, dh0?h31, tbst , tsiz0?siz2. input valid to sysclk (input setup) 2.5 ns 2 12 hit , ts , ar tr y , br0 , br1 , xa ts input signals valid to sysclk (input setup) 5.0 ns 3 13 mode select inputs valid to hrst (input setup) 3 * t sys ns 4, 5 14 lock , flshreq , isa_master , c/be0 c/be 3 , par, trdy , irdy , frame , st op , devsel , perr , serr , ad0?d31 input signals valid to sysclk (input setup) 7.0 ns 6 15 pci point-to-point signals input signals valid to sysclk (input setup) 10.0 ns 7 16 sysclk to inputs invalid (input hold) 1.0 ns 1?, 17 sysclk to pci inputs invalid (input hold) 0.0 ns 6,7 18 hrst to mode select inputs invalid (input hold) 1.0 ns 4, 8 notes: all input speci?ations are measured from the ttl level (0.8 or 2.0 v) of the signal in question to the 1.4 v of the rising edge of sysclk. processor and memory interface signals are speci?d from the rising edge of the processor and memory bus clock, which is the same as sysclk in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of sysclk). both input and output timings are measured at the pin. 1. inputs are composed of the following processor interface signals?0?31, par0?ar7, tt0?t4, aack , t a , gbl , ci , wt , tv. 2. inputs are composed of the following processor interface signals?l0?l31, dh0?h31, tbst , tsiz0?siz2. 3. inputs are composed of the following processor and l2 interface signals?it , ts , ar tr y , br0 , br1 , xa ts . 4. the setup and hold time is with respect to the rising edge of hrst ; see figure 3. the following signals encompass the mode (or con?uration) pins for mpc105?cs0 , bctl0 , dl0, xa ts , and fnr. 5. t sys is the period of the external clock (sysclk) in nanoseconds 6. inputs are composed of all pci bus signals: lock , flshreq , isa_master , c/be0 ?/be3 , par, trdy , irdy , frame , st op , devsel , perr , serr , ad0?d31. 7. inputs are composed of all pci point-to-point signals. gnt has a setup time of 10.0 ns for a 33 mhz pci clock. 8. guaranteed by design, not tested.
8 105 hardware specifications preliminary/subject to change without notice figure 2. input timing diagram figure 3. mode select input timing diagram 1.3.2.3 output ac speci?ations table 7 provides the output ac timing speci?ations for the mpc105 as de?ed in figure 4. these speci?ations are for operation between 16.67 mhz and 33.33 mhz bus clock (sysclk) frequencies . table 7. output ac timing specifications vdd = 3.3 5% vdc, gnd = 0 vdc num characteristic min max unit notes 19 sysclk to output driven (output enable time) 2.0 ns 20 sysclk to output valid (for pci bus signals) 11 ns 1, 2, 3 21 sysclk to output valid (for pci point-to-point signals) 12 ns 1, 2, 4 22 sysclk to output valid (for ts , ar tr y , all non-pci signals except tale, baa , ras /cs0 ?as /cs7 , cas / dqm0?as /dqm7) 8.0 ns 1, 2, 7 23 sysclk to output valid (for tale, baa ) 10.0 ns 1, 2 24 sysclk to output valid (for ras /cs0 ?as /cs7 , cas /dqm0?as /dqm7) 9.0 ns 1, 2 14?6 vm vm = midpoint voltage (1.4 v) sysclk 10?2 all inputs vm vm = midpoint voltage (1.4 v) hrst 16 mode pins 13
105 hardware specifications 9 preliminary/subject to change without notice 25 sysclk to output invalid (output hold) 0.0 ns 26 sysclk to output high impedance (all except ar tr y ) 8.0 ns 27 sysclk to ar tr y high impedance before precharge (output hold) 8.0 ns 28 sysclk to ar tr y precharge enable (1x, 2x, pll mode) 0.4 * t sys + 2.0 ns 5, 6 29 precharge width for ar tr y 1.0 t sys 5, 6 30 sysclk to ar tr y high impedance after precharge (1x, 2x pll modes) 1.5 * t sys + 8.0 ns 5 notes: all output speci?ations are measured from the ttl level (0.8 v or 2.0 v) of the signal in question to the 1.4 v of the rising edge of sysclk. processor and memory interface signals are speci?d from the rising edge of the processor and memory bus clock, which is the same as sysclk in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of sysclk). both input and output timings are measured at the pin. 1. all output speci?ations are measured from the 1.4 v of the rising edge of sysclk to the ttl level (0.8 v or 2.0 v) of the signal in question. the output timings are measured at the pin. 2. maximum timing speci?ations assume c l = 50 pf. 3. pci bus signals are composed of the following signals?ock , memack , isa_master , c/be0 ?/be3 , par, trdy , frame , st op , devsel , perr , serr , and ad0?d31. 4. pci point-to-point signals are composed of the gnt signal. 5. t sys is the period of the external bus clock (sysclk) in nanoseconds. the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in nanoseconds) of the parameter in question. 6. these speci?ations are nominal values. 7. shared outputs, ts and ar tr y , require pull-up resistors to hold them negated when there is no bus master driving. table 7. output ac timing specifications (continued) vdd = 3.3 5% vdc, gnd = 0 vdc num characteristic min max unit notes
10 105 hardware specifications preliminary/subject to change without notice figure 4. output timing diagram 1.3.3 jtag ac timing speci?ations table 8 provides the jtag ac timing speci?ations. table 8. jtag ac timing specifications (independent of sysclk) num characteristic min max unit tck frequency of operation 0 25 mhz 1 tck cycle time 40 ns 2 tck clock pulse width measured at 1.5 v 20 ns 3 tck rise and fall times 0 3 ns 4 trst setup time to tck falling edge 10 ns 5 trst assert time 10 ns 6 boundary-scan input data setup time 5 ns 7 boundary-scan input data hold time 15 ns 8 tck to output data valid 0 30 ns 9 tck to output high impedance 0 30 ns 10 tms, tdi data setup time 5 ns 11 tms, tdi data hold time 15 ns 12 1 tck to tdo data valid 0 15 ns sysclk 19 23 22 25 26 26 all outputs (except ts , ar tr y ) ts ar tr y vm vm vm = midpoint voltage (1.4 v) 25 vm 22 29 27 28 30 21 20 24
105 hardware specifications 11 preliminary/subject to change without notice figure 5 provides the jtag clock input timing diagram. figure 5. clock input timing diagram figure 6 provides the trst timing diagram . figure 6. trst timing diagram figure 7 provides the boundary-scan timing diagram. figure 7. boundary-scan timing diagram 13 1 tck to tdo high impedance 0 15 ns note: 1. load capacitance = 20 pf table 8. jtag ac timing specifications (independent of sysclk) (continued) num characteristic min max unit tck 2 2 1 vm vm vm 3 3 vm = midpoint voltage 4 5 trst tck 6 7 input data valid 8 9 8 output data valid output data valid tck data inputs data outputs data outputs data outputs
12 105 hardware specifications preliminary/subject to change without notice figure 8 provides the test access port timing diagram. figure 8. test access port timing diagram 10 11 input data valid 12 13 12 output data valid output data valid tck tdi, tms tdo tdo tdo
105 hardware specifications 13 preliminary/subject to change without notice 1.4 mpc105 pinout diagram figure 9 contains the pin assignments for the mpc105. figure 10 provides a key to the shading in figure 9. figure 10. pin assignments shading key 16151413121110987654321 w dl26 dl28 dl30 dh31 dh29 dh27 dh25 dh23 dh21 dh19 dh17 dh15 dh13 dh11 dh9 dh7 w v dl24 dl27 dl29 dl31 dh30 dh28 dh26 dh24 dh20 dh18 dh16 dh14 dh12 dh10 dh8 dl22 v u ma0 dl23 dl25 dl14 pll2 pll0 dl12 dl10 dl4 dl2 dl0 doe dbg1 dh6 dl21 dl20 u t ma1 we dh0 dl15 pll3 pll1 dl13 dl11 dl3 dl1 tv t aloe hit br1 dl19 tale t r ma2 rcs0 dh2 dh1 dl16 vss vdd dl9 dl5 vss vdd twe bg1 ads a0 ts r p ma4 ma3 dh4 dh3 vss vdd vss dl8 dl6 vdd vss vdd baa dwe a1 xa ts p n ma5 dwe7 dl17 dh5 vdd vss vdd dl7 dh22 vss vdd vss dwe2 ci a2 t a n m ma7 ma6 ras/cs0 dl18 vss vdd vss nc nc vdd vss vdd wt gbl a3 tt4 m l hrst ma8 qack ras/cs1 vdd dwe3 ras /cs5 vss vdd vss sysclk dbg0 tbst br0 a4 tt3 l k ma10 ma9 ras/cs3 ras/cs2 ras/cs4 ras/cs7 vdd avdd vss vdd a9 a8 a7 bg0 a5 tt2 k j ma11 cas /dqm0 sdras dwe0 ras/cs6 mcp dwe4 vss vdd vss a11 a6 a13 a12 a10 tea j h qreq cas /dqm1 suspend trst vss dwe6 dwe5 nc nc vdd vss vdd a15 a14 a16 tt1 h g cas /dqm2 rtc cas /dqm4 cas /dqm5 vdd lssd_mode vdd par lock vss vdd vss tsiz1 tsiz0 a17 tt0 g f bctl0 bctl1 cas /dqm6 tck vss vdd vss perr devsel vdd vss vdd a21 tsiz2 ar tr y a18 f e cas /dqm3 nmi cas /dqm7 sdcas tdo vss vdd serr irdy vss vdd a31 a29 a22 a20 a19 e d par0 par1 tms foe /rcs1 ad28 ad24 ad21 ad17 ad14 ad10 c/be0 ad4 ad0 a30 aack a23 d c par2 par3 par5 ad30 ad26 ad23 ad19 c/be2 c/be1 ad12 ad8 ad6 ad2 a27 a25 a24 c b par4 par7 ad1 tdi ad7 ad11 ad15 trdy ad18 ad22 ad25 ad29 req isa_master a28 a26 b a par6 gnt ad3 ad5 ad9 ad13 frame st op ad16 ad20 c/be3 ad27 ad31 flshreq memack a 16151413121110987654321 figure 9. pin assignments nc vss vdd no connect power supply ground power supply positive avdd clock power supply positive (k9) view signals
14 105 hardware specifications preliminary/subject to change without notice table 9 provides the pinout listing for the mpc105. table 9. pinout listing 1 signal name pin number active i/o 60x processor interface signals a0?31 r2, p2, n2, m2, l2, k2, j5, k4, k5, k6, j2, j6, j3, j4, h3, h4, h2, g2, f1, e1, e2, f4, e3, d1, c1, c2, b1, c3, b2, e4, d3, e5 high i/o aack d2 low i/o ar tr y f2 low i/o br0 l3 low input bg0 k3 low output br1 (dir ty_in ) t3 low input bg1 (dir ty_out ) r4 low output ci n3 low i/o dbg0 l5 low output dbg1 (t oe ) u4 low output dh0?h31 t14, r13, r14, p13, p14, n13, u3, w1, v2, w2, v3, w3, v4, w4, v5, w5, v6, w6, v7, w7, v8, w8, n8, w9, v9, w10, v10, w11, v11, w12, v12, w13 high i/o dl0?l31 u6, t7, u7, t8, u8, r8, p8, n9, p9, r9, u9, t9, u10, t10, u13, t13, r12, n14, m13, t2, u1, u2, v1, u15, v16, u14, w16, v15, w15, v14, w14, v13 high i/o gbl m3 low i/o t a n1 low i/o tbst l4 low i/o tea j1 low output ts r1 low i/o tsiz0?siz2 g3, g4, f3 high i/o tt0?t4 g1, h1, k1, l1, m1 high i/o wt m4 low i/o xa ts p1 low input
105 hardware specifications 15 preliminary/subject to change without notice pci interface signals c/be 0 ?/be3 d6, c8, c9, a6 low i/o devsel f8 low i/o flshreq a3 low input frame a10 low i/o irdy e8 low i/o isa_master b3 low input lock g8 low input memack a2 low output ad0?d31 d4, b14, c4, a14, d5, a13, c5, b12, c6, a12, d7, b11, c7, a11, d8, b10, a8, d9, b8, c10, a7, d10, b7, c11, d11, b6, c12, a5, d12, b5, c13, a4 high i/o par g9 high i/o gnt a15 low input req b4 low output perr f9 low i/o serr e9 low i/o st op a9 low i/o trdy b9 low i/o l2 cache interface signals ads r3 low output baa p4 low output dir ty_in (br1 ) t3 low input dir ty_out (bg1 ) r4 low output doe u5 low output dwe0 (fnr) j13 low output dwe (dwe1 ) p3 low output dwe2 n4 low output table 9. pinout listing 1 (continued) signal name pin number active i/o
16 105 hardware specifications preliminary/subject to change without notice dwe3 (cko) l11 low output dwe4 j10 low output dwe5 h10 low output dwe6 h11 low output dwe7 (cke) n15 low output hit t4 low input tale t1 high output t aloe t5 low output t oe /dbg1 u4 low output tv t6 high i/o twe r5 low output memory interface signals bctl0 f16 low output bctl1 f15 low output cas /dqm0?as /dqm7 j15, h15, g16, e16, g14, g13, f14, e14 low output cke/dwe7 n15 high output foe /rcs1 d13 low output ma0?a11 (ar0?r11) u16, t16, r16, p15, p16, n16, m15, m16, l15, k15, k16, j16 high output par0?ar7 (ar0?r7) d16, d15, c16, c15, b16, c14, a16, b15 high i/o ras/cs0 ?as/cs7 m14, l13, k13, k14, k12, l10, j12, k11 low output rcs0 r15 low i/o rtc g15 high input sdcas e13 low output sdras j14 low output we t15 low output table 9. pinout listing 1 (continued) signal name pin number active i/o
105 hardware specifications 17 preliminary/subject to change without notice interrupt, clock, and power management signals ck0/dwe3 l11 high output hrst l16 low input mcp j11 low output nmi e15 high input qack l14 low output qreq h16 low input sysclk l6 clock input suspend h14 low input test/con?uration signals fnr/dwe0 j13 high input pll0?ll3 u11, t11, u12, t12 high input tck f13 clock input tdi b13 high input tdo e12 high output tms d14 high input trst h13 low input power and ground signals avdd k9 high clock power vdd e10, e6, f11, f5, f7, g10, g12, g6, h5, h7, k10, k7, l12, m11, m5, m7, n10, n12, n6, p11, p5, p7, r10, r6, j8, l8 high power lssd_mode 2 g11 low input vss e11, e7, f10, f12, f6, g5, g7, h12, h6, j7, l7, m10, m12, m6, n11, n5, n7, p10, p12, p6, r11, r7, k8, j9, l9 low ground nc h8, h9, m8, m9 note: 1. some signals have dual functions and are shown more than once in this table. 2. this test signal is for factory use only. it must be pulled up to vdd for normal machine operation. table 9. pinout listing 1 (continued) signal name pin number active i/o
18 105 hardware specifications preliminary/subject to change without notice 1.5 mpc105 package description the following sections provide the package parameters and the mechanical dimensions for the mpc105. 1.5.1 package parameters the package parameters are as provided in the following list. the package type is a 21 mm x 25 mm, 304- pin c4 ceramic ball grid array (cbga). package outline 21 mm x 25 mm interconnects 303 pitch 1.27 mm solder attach 63/37 sn/pb solder balls 10/90 sn/pb maximum module height 3.16 mm co-planarity speci?ation 0.20 mm
105 hardware specifications 19 preliminary/subject to change without notice 1.5.2 mechanical dimensions figure 11 shows the mechanical dimensions for the mpc105. figure 11. mpc105 mechanical dimensions 2.5 mm b a p c a1 0.200 2x 0.200 2x ?e ?f 0.200 ?t t h n g k ? 0.300 12 345678910111213141516 w v u t r p n m l k j h g f e d c b a 303x ? d s t s e s f ? 0.300 s t *not to scale note: all measurements are in mm. min max a 25.0 basic b 21.0 basic c 2.3 3.16 d 0.82 0.93 g 1.27 basic h 0.79 0.99 k 0.635 basic n 5.8 6.3 p 6.7 6.9 top view
20 105 hardware specifications preliminary/subject to change without notice 1.6 system design information this section provides electrical and thermal design recommendations for successful application of the mpc105 pci bridge/memory controller. 1.6.1 pll con?uration the mpc105 is designed to operate over a wide range of processor and pci bus frequencies. the pll is con?ured by the pll_cfg0?ll_cfg3 pins. for a given sysclk (bus) frequency, the pll con?uration pins set the internal mpc105 frequency of operation. table 10 describes the pll con?urations required for different ratios between the processor bus frequency and the pci bus frequency. table 10. pll configuration notes: 1. some pll con?urations may select bus, cpu, or pll frequencies which are not useful, not supported, or not tested for by the mpc105. pll frequencies (shown in parenthesis in table 10) should not fall below 120 mhz, and should not exceed 200 mhz. 2. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, and the bus is set for 1:1 mode operation. the pll-bypass mode is for test only, and is not intended for functional use. in clock-off mode, no clocking occurs inside the mpc105 regardless of the sysclk input. 3. the pll_cfg0?ll_cfg1 signals select the cpu-to-bus ratio (1:1, 2:1) and the pll_cfg2?ll_cfg3 signals select the pci-to-pll multiplier (x2, x4, x8). 4. the level 2 cache and memory interfaces will function at the processor bus frequency. 1.6.2 pll power supply filtering the avdd power signal is provided on the mpc105 to provide power to the clock generation phase-lock loop. to ensure stability of the internal clock, the power supplied to the avdd input signal should be ?tered using a circuit similar to the one shown in figure 12. the circuit should be placed as close as possible to the avdd pin to ensure it ?ters out as much noise as possible. pll_cfg0?ll_cfg3 processor bus, pci, and pll frequencies processor bus: pci bus ratio (sysclk) pci bus 16.6 mhz pci bus 20 mhz pci bus 25 mhz pci bus 33.3 mhz 0001 1:1 33.3 (133) 0010 1:1 16.6 (133) 20 (160) 25 (200) 0100 2:1 66.6 (133) 0101 2:1 33.3 (133) 40 (160) 50 (200) 0011 pll bypass 1111 clock off
105 hardware specifications 21 preliminary/subject to change without notice figure 12. pll power supply filter circuit 1.6.3 decoupling recommendations the mpc105 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the mpc105 system, and the mpc105 itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer place a decoupling capacitor with a low esr (effective series resistance) rating to at least one vdd pin of the mpc105. this capacitor should be at least 0.1 m f to provide both high and low frequency ?tering, and should be placed as close as possible to their associated vdd pin. surface-mount tantulum or ceramic devices are preferred. it is also recommended that these decoupling capacitors receive their power from vdd and gnd power planes in the pcb, utilizing short traces to minimize inductance in the traces. power and ground connections must be made to all external vdd and gnd pins of the mpc105. 1.6.4 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active-low inputs should be connected to vdd. unused active-high inputs should be connected to gnd. note that in 32-bit data bus mode, the unused processor bus data signals (dl0-dl31) must be connected to pull-up resistors for proper device operation. 1.6.5 mpc105 thermal management information the use of c4 die on a cbga interconnect technology offers signi?ant reduction in both the signal delay and the microelectronic packaging volume. figure 13 shows the salient features of the c4/cbga interconnect technology. the c4 interconnection provides both the electrical and the mechanical connections for the die to the ceramic substrate. after the c4 solder bump is re?wed, epoxy (encapsulant) is under-?led between the die and the substrate. under-?l material is commonly used on large high-power die; however, this is not a requirement of the c4 technology. the package substrate is a 21 mm multilayer- co?ed ceramic. the package-to-board interconnection is by an array of orthogonal 90/10 (lead/tin) solder balls on 1.27 mm pitch. during assembly of the c4/cbga package to the board, the high-melt balls do not collapse. figure 13. exploded cross-sectional view vdd avdd 10 ohms 10 uf 0 . 1 uf gnd chip with c4 encapsulant ceramic substrate cbga joint printed-circuit board
22 105 hardware specifications preliminary/subject to change without notice 1.6.5.1 internal package conduction resistance for this c4/cbga packaging technology, the intrinsic conduction thermal resistance paths are as follows: the die junction-to-case thermal resistance the die junction-to-lead thermal resistance these parameters are shown in table 11. in this c4/cbga package, the silicon chip is exposed; therefore, the package ?ase?is the top of the silicon. figure 14 provides a simpli?d thermal network in which a c4/cbga package is mounted to a printed- circuit board. figure 14. c4/cbga package mounted to a printed-circuit board 1.6.5.2 board and system-level modeling a common ?ure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies is the junction-to-ambient thermal resistance. the ?al chip-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. in addition to the components power dissipation, a number of factors affect the ?al operating die-junction temperature. for example, these factors might include air?w, board population, heat sink ef?iency, heat sink attach, next-level interconnect technology, and system air temperature rise. table 11. thermal resistance thermal metric effective thermal resistance junction-to-case thermal resistance 0.133 c/w junction-to-lead (ball) thermal resistance 3.8 c/w external resistance external resistance secondary heat transfer path primary heat transfer path internal resistance (note the internal versus external package resistance) radiation convection radiation convection heat sink silicon c4 package printed-circuit board heat sink attach package leads/ball chip junction under?l
105 hardware specifications 23 preliminary/subject to change without notice due to the complexity and the many variations of system-level boundary conditions for todays microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary widely. for this reason, we recommend using conjugate heat transfer models for the board as well as system-level designs. to expedite system-level thermal analysis, several ?ompact cbga thermal models are available within flotherm . these are available upon request. the die junction-to-ambient thermal resistance is shown in table 12. the model results are in accordance with semi speci?ation g38. this standard speci?s a single component be placed on a 7.5 cm x 10 cm single-layer printed-circuit card. note that this single metric may not adequately describe three-dimensional heat ?w. table 12. die junction-to-ambient thermal resistance air?w velocity (meter/second) air?w velocity (feet/minute) die junction-to-ambient thermal resistance (semi g38) ( c/w) 1 196.8 22.0 2 393.7 18.5 3 590.0 17.0
information in this document is provided solely to enable system and software implementers to use powerpc microprocessors. there are no express or implied copyright licenses granted hereunder to design or fabricate powerpc integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical?parameters can and do vary in different applications. all operating parameters, including ?ypicals?must be validated for each customer application by customer? technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af?mative action employer. ibm is a registered trademark of ibm corp. the powerpc name, powerpc logotype, powerpc architecture, powerpc 603, and powerpc 604 are trademarks of international business machines corp. used by motorola under license from ibm corp. motorola literature distribution centers: usa: motorola literature distribution, p.o. box 20912, phoenix, arizona 85036; fax (602) 994-6430. japan: nippon motorola ltd., 4-32-1, nishi-gotanda, shinagawa-ku, tokyo 141 japan. asia-pacific: motorola semiconductors h.k. ltd., silicon harbour centre, no. 2 dai king street, tai po industrial estate, tai po, n.t., hong kong. technical information : motorola inc. semiconductor products sector technical responsiveness center; (800) 521-6274. document comments : fax (512) 891-2638, attn: risc applications engineering.

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